As semiconductor devices continually progress towards denser packing of active devices, isolation between active devices having the same conductivity type, such as n-channel metal oxide semiconductors (NMOS) or p-channel metal oxide semiconductors (PMOS) used as field effect transistors, becomes an extremely important issue.
Less densely packed integrated circuits (ICs) could rely on isolation by a thick field oxide, scaling technology now, however demands less isolation space between active devices (i.e., adjacent NMOS transistors) than that required when using field oxide. In response to this demand, much of the MOS fabrication now uses trench isolation between active devices.
Typically, trench isolation comprises the etching of a trench into the substrate (i.e., silicon, gallium arsenide, etc.) thereby separating adjacent devices having like conductivity. The trench is then filled, usually with oxide.
One of the problems with trench isolation is preventing a step-down at the edge of the trench into the field regions. This step causes a resulting sidewall parasitic device (resident at the trench sidewall formed between the gate poly as it crosses onto the field oxide and the sidewall of the trench.) to turn on sooner than the bulk device (i.e., NMOS device) itself. Also, the gate oxidation over the step-down is thinner, thereby degrading the reliability of the gate oxide. Finally, doping of the sidewall of the trench to increase the Vt. of the parasitic sidewall device is difficult, in that it requires either high-angled implants or some type of in-diffusion from the poly or a furnace doping process of some kind.